The present invention relates to a semiconductor technology; and, more particularly, to a method for aligning an optical device with an optical fiber and a planar lightwave circuit (PLC) by using a passive alignment method.
There is a need for an exact alignment between optical axes to get the maximum optical coupling between optical devices such as an optical fiber and a laser diode (LD) Conventionally, when the laser diode is aligned with an optical device, it is required that the tolerance of the optical alignment accuracy is within about 1 xcexcm. In general, the alignment method is classified into an active alignment and a passive alignment. The active alignment is a method of achieving an optimum alignment by controlling the position of the optical waveguide and the LD based on the intensity observed with turning on the LD. This method can provide an optimum optical alignment easily, however, it is expensive to implement due to its complex process. Whereas the passive alignment is a method of carrying out the alignment of the optical axes with turning off the LD. In this method, it is difficult to obtain an optimum alignment of the optical axes, however, it is cost-effective due to its simple structure.
The passive alignment method is further classified into three methods as follows:
The first is a mechanical alignment method that optical devices are mounted on a silicon substrate after cutting grooves exactly to have the optical devices mounted on the silicon substrate and to fabricate the optical devices in an exact dimension. In this method, it is difficult that the optical devices and the silicon substrate are fabricated to have the tolerance of the optical alignment accuracy within about 1 xcexcm.
The second is a flip-chip bonding method through the use of the surface tension of solder bumps that the solder bumps on the silicon substrate and solder pads on the optical device are exactly formed on their corresponding positions, respectively, by a conventional photolithography method. After the solder pads are aligned with the solder bumps, and then they are heated, the solder bumps are reflowed to be changed into the most stable shape and have the optical devices exactly positioned. However, in this method the reflow condition of the solder bumps is strict and it is required to prevent the oxidation of the solder.
Finally, the third is a mask alignment method that can be referred as the prototype of this invention, which alignment marks are formed on the silicon substrate and the optical devices and the optical devices are aligned with the substrate by using the alignment marks, this method will be described in detail hereinbelow.
FIG. 1a is an exemplary cross sectional view illustrating a method of connecting a laser diode to an optical fiber by using a conventional mark alignment method, FIG. 1b represents a plan view of a laser diode and FIG. 1c is a plan view of a substrate.
Referring to the drawings, a silicon wafer 10 is generally used as a substrate and a V-shaped groove 11 is used for clamping an optical fiber. The V-shaped groove 11 is obtained by wet-etching a silicon single crystal in KOH solution. The silicon single crystal has a different etching rate according to its crystalline plane, that is, since an etching ratio between a crystalline plane 111 and the other crystalline plane is in the order of 1/100, it is possible to obtain the V-shaped groove with a predetermined angle, e.g., 54.7xc2x0, after the etching is carried out for enough period of time, wherein the predetermined angle is an angle between the surface of the substrate and the surface of the V-shaped groove. Once the V-shaped groove 11 is formed, in case that it is still immersed in the KOH solution, the angle of the V-shaped groove 11 is hardly changed due to its negligible etching amount.
As shown in FIG. 2a, a silicon wafer 20 of crystalline plane 100 is generally used, after being etched by KOH solution, to obtain an angle of 54.7xc2x0 between the surface of the silicon wafer 20 and an exposed crystalline plane 100. Typically, a process for forming the V-shaped grooves A, B is as follows: first, depositing on top of the silicon wafer 20 a material such as a silicon nitride (Si3N4) layer and a silica layer (SiO2) and the like which does not react with KOH solution; selectively removing portions of the material where the V-shaped grooves are to be formed, to thereby form a V-shaped etching window; and immersing the silicon wafer 20 into KOH solution, thereby forming the V-shaped grooves A, B under the removed portions of the material. At this time, the width and the depth of the V-shaped grooves A, B are determined by the width of the V-shaped etching window. After two windows are formed on the silicon wafer 20, each window having a different width, and by etching the silicon wafer 20 in KOH solution, the V-shaped grooves A, B in FIG. 2a can be obtained, simultaneously. In this case, the V-shaped groove B of the small window width is first formed and even though it is still immersed into KOH solution until the V-shaped groove A of the large window width is formed, the V-shaped groove B is not being etched further. Therefore, a width and a depth of a V-shaped groove can be obtained by controlling a window width. Thereafter, as shown in FIG. 2b, an optical fiber 22 can be exactly aligned by positioning it on a V-shaped groove 23.
Referring back to FIGS. 1a to 1c, there are alignment marks 13a, 13b for defining a position of an optical device such as a LD 12. After cross-shaped marks 13a, 13b are formed on the silicon substrate 10 and the LD 12, respectively, these marks 13a, 13b are aligned by using an optical apparatus such as a microscope to fix the LD 12. FIG. 3 is a view exemplifying a method for aligning an optical device 31 with a silicon substrate 30 by using an infrared ray, which has low attenuation in a substrate 30 and optical device 31. The reference numerals 32 and 33 represent the alignment marks and the objective lens of the microscope, respectively.
Further, a plurality of solder bumps 14 and metal pads 7 can be provided on an upper surface of the silicon wafer 10 to attach the LD 12 to the silicon wafer 10 and to apply electrical signals to the LD 12. As shown in FIG. 1a, there is a under bump metallurgy (UBM) 15 for bonding the solder bump 14 to the silicon wafer 10 and a solder dam 16 made of a material such as silicon nitride which is non-adhesive to the solder bump 14. The LD 12 is electrically connected to the metal line 17 through the use of the solder bump 14. Also, a Au support 8 is formed to match a height of a core 18 of the LD 12 to that of a core 9 of the optical fiber 19.
As described hereinabove, the passive alignment method for aligning an optical device and optical fiber and the passive alignment for aligning an optical device and a PLC is well known, however, the passive alignment of three devices, e.g., the laser diode, the PLC and the optical fiber, is very difficult.
On the other hand, the prior art method employs a metal layer to obtain an optical contrast for the alignment mark. As shown in FIG. 4, since a structure of silicon PLC 41 based on a silicon substrate 40 has a non-planarized surface due to a step caused by its structure, it is impossible to obtain a planarized surface by spin-coating a thin photoresist on top of the non-planarized surface. Therefore, it is required that a very thick photoresist 42 should be coated on top of the non-planarized surface to obtain a planarized surface of the photoresist 42. Alignment marks 43a are formed by a lift-off method as follows: selectively removing portions of photoresist 42 where the alignment marks 43a are formed; depositing a metal layer 43 on top of the photoresist 42; and removing the photoresist 42.
Since, however, the very thick photoresist 42 is used as a mask in this method, there is a shortcoming in accuracy.
In the conventional method, the formation of V-shaped grooves is as follows: depositing on top of a silicon wafer the mask layer such as a silicon nitride layer which does not react with KOH solution; selectively removing portions of the mask layer where the V-shaped grooves are formed, thereby producing etching widows; and etching the silicon wafer by using KOH solution.
However, in case that the structure has a PLC with a non-planarized surface, since the thickness of the photoresist must be thick enough to pattern the V-shaped grooves, it is very difficult that the V-shaped grooves are exactly formed in place.
It is, therefore, an object of the present invention to provide a passive alignment method for facilely ensuring an alignment accuracy of optical device without being affected by the non-uniform surface which is formed during the formation of V-shaped grooves for use in aligning an optical fiber with a silicon substrate. Another object of the present invention is to provide a method for assembling an optical device, a planar lightwave circuit (PLC) and an optical fiber by using a passive alignment capable of passive-aligning the optical device, the PLC and the optical fiber, simultaneously.
In accordance with one aspect of the present invention, there is provided a method for aligning optical devices with a silicon substrate by using a passive alignment, the method comprising the steps of: (a) etching a portion of the silicon substrate in a predetermined thickness, wherein a remaining portion of the silicon substrate is used for the formation of a plurality of V-shaped grooves; (b) forming a mask layer on the silicon substrate and planarizing the mask layer; (c) etching back the mask layer to expose the silicon substrate, thereby forming an etching mask pattern for use in the formation of the V-shaped grooves; (d) etching the exposed silicon substrate until a sidewall of the etching mask pattern is open; and (e) wet-etching the silicon substrate by using the etching mask pattern as an etching barrier to thereby forming the V-shaped grooves.
In accordance with another aspect of the present invention, there is a method for aligning an optical device, an optical fiber and a planar lightwave circuit (PLC) with each other by using a passive alignment, the method comprising the steps of: (a) preparing a silicon substrate provided with an alignment mark region, an electrode region and an optical fiber alignment region and etching a remaining portion of the silicon substrate except those regions in a first preset thickness; (b) selectively etching a region of the silicon substrate, on which a lower clad layer of the PLC is formed, in a second preset thickness; (c) forming a silica layer on top of the silicon substrate for forming a lower clad layer of the PLC; (d) etching back the silica layer, thereby forming the lower clad layer by burying the silica layer in the region; (e) forming a core and upper layers of the planar lightwave circuit subsequently and patterning the core and the upper layers into a predetermined pattern, thereby providing the PLC; (f) etching the silicon substrate until a portion of a sidewall of the silica layer buried in the region is exposed; (g) wet-etching the silicon substrate by using the silica layer as an etching barrier to form a first set of V-shaped grooves for serving as an alignment mark, a second set of V-shaped grooves for aligning solder bumps and a third set of V-grooves for aligning the optical fiber; (h) forming solder bumps in the second set of V-grooves; and (i) assembling the optical device and the optical fiber on the silicon substrate.